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Date: 28-05-14

Reliability enhanced wafer scale package by STATS ChipPAC

Semiconductor device packaging expert STATS ChipPAC has added thin protective coating on the four sidewalls of the silicon die, and the package is called as encapsulated Wafer Level Chip Scale Package (eWLCSP), a better alternative to Wafer Level Chip Scale Packaging (WLCSP). Wafer scale packaging is popular due to its space-saving and also sometimes cost saving benefits. But the Wafer scale package is prone to damage during the surface mount technology (SMT) process.
In this deep node age, the WLCSP design becomes even more of a concern due to the fragile dielectric layers.

"WLCSP is a bare die package that is constantly exposed to potential cracking, chipping and handling damages before or during the SMT process. This is particularly true for advanced node products where the die is very thin and dielectric layers are extremely fragile," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. "As mobile device manufacturers tighten their technical specifications to reach new levels of reliability in their products, the industry will see more stringent component level and board level reliability (BLR) requirements. eWLCSP is a robust packaging solution that cost effectively addresses the increased durability requirements for our customers in advanced silicon nodes down to 28nm."

STATS ChipPAC says "the significant benefit of encapsulation is the light and mechanical protection for the bare die. The protective layer also safeguards the silicon during socket insertion for test. eWLCSP delivers electrical performance that is equivalent to standard WLCSP with proven results in component level reliability (CLR), temperature cycle on board (TCoB) and drop test."

STATS ChipPAC uses a manufacturing method called FlexLine to process multiple silicon wafer diameters in the same manufacturing line and produce both fan-out and fan-in packages. The FlexLine process has been qualified at advanced silicon nodes down to 28nm, ball pitches down to 0.40mm and body sizes as small as 2.5x2.5mm.

Dr. Han continued, "FlexLine is a strong manufacturing platform that enables unique technology enhancements such as eWLCSP and a cost effective manufacturing approach to wafer level packaging. Using the FlexLine method, 200mm incoming wafers can be reconstituted into 300mm or larger panel sizes, providing customers with significant per unit cost reduction as the panel size increases. In addition, a conventional WLCSP can be converted to eWLCSP without any silicon design change required, regardless of the current silicon wafer diameter."

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