eASIC and MoSys have announced successful hardware interoperability at 10.3125 Gbps and 12.5 Gbps between the MGIO (Multi Gigabit I/O) serial transceivers on eASIC’s Nextreme-3 28nm family and the CEI-11 compatible interface on the MoSys Bandwidth Engine IC.
GigaChip Interface by MoSys is suitable for any chip-to-chip interconnect. The GigaChip Interface deliver up to 180 Gbps of full duplex throughput using 16 SerDes lanes when running at a 12.5 Gbps rate.
GigaChip Interface consumes less than 3% of the eASIC Nextreme-3 N3XT1800 device.
“We are seeing a major trend towards high speed serial chip-to-chip interconnect which is driven by the system requirements for 40 G, 100 G and beyond”, said Jasbinder Bhoot, vice president of worldwide marketing at eASIC. “The combination of our ability to deliver high performance, low NRE and fast-time to market ASIC devices and the GigaChip Interface benefits of reduced complexity, power and cost, solves the system memory bandwidth limitations in 100G+ carrier-class and enterprise equipment.”
“eASIC is a leader in single mask ASICs and we are pleased to have its support of the GigaChip Interface for its networking customers.” said John Monson, VP of marketing and sales for MoSys. “Leveraging the GigaChip Interface with the Bandwidth Engine accelerated memory access and offload capabilities combined with the eASIC Nextreme-3 arrays, our mutual customers will be able to deliver differentiated high performance networking solutions in less time, using less space and at lower cost.”