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  Date: 25/05/2014

Chip design: Faster and simpler automatic VLSI layout creator

SoC design software vendor Pulsic developed automated layout software for transistor-level layout-design for complex VLSI design, which the company claims as better than manual-quality checked layout.

The product called Pulsic Animate is automated layout system delivering multiple layouts from a schematic diagram by using automatic constraint extraction and also does place and route concurrently.

Animate saves VLSI design engineer from manual constraint entry and management by automatically generating constraint based netlist topology and analysis. Animate derives different variations of layout designs by using a patented technology called polymorphic layout with a database and algorithmic architecture. Animate is said to create DRC/LVS-correct layouts in minutes. By using this tool, VLSI designers can generate layouts at a fraction of time compared to the manual-quality layout option, according to Pulsic.

This tool also makes parasitics available for simulation early in the design due to faster layout creation. Animate does the place and route tasks simultaneously by using polymorphic layout, and generates all the possible layouts and solutions and skip those that does not fit designer's criteria, so that the best layout is only selected.

“As geometries shrink, and as leading-edge processes such as FinFETS reach the market, manual analog design is no longer sufficient,” said Mark Williams, co-founder and CEO, Pulsic. “To get routable placement, you need to know what the routing will look like, but if you place and then route, you can’t know this. As DRC rules increase, iterations between layout and design are becoming onerous, but with Animate, you can generate multiple layouts, extract them all, and then choose the optimal one for the desired performance criteria. A much bigger problem space can be explored, with better results”

The chip designers are guided through a GUI to visualize layout options. During the process constraints are derived automatically and they can be edited by the engineer in faster and easier manner.

Animate can be employed at the early stage of the SoC/IC design, so that the designer can explore all the possible layout options with minimal constraints and also extract the parasitics at the early stage of layout dependent effects (LDE). This approach set to benefit the designer in floor planning of analog blocks more accurately.

Pulsic compares this tool to a highly efficient manual layout process but only difference being it is faster and simpler.

To inform you another interesting development in this area, Concept Engineering has introduced a tool called S-engine as part of its NIView chip design software platform. S-engine does automatic schematic generation that allows visualization at higher levels of abstraction. S-engine allows Nlview users to have smart editing capabilities at the system level.

Concept engineering says its S-engine's automatic schematic generation allows visualization at higher levels of abstraction, such as interface connections and intelligent IP-on-the-fly management, to easily handle configurable IP building blocks. Smart editing capabilities allow the creation of new and innovative SoC, network-on-chip (NoC) and IP design tools.

"As design complexity continues to grow and design teams use more and more in-house or third-party IP as part of their SoC, NoC or IP creation, the need for visualization and design technology at the IP level and system level becomes increasingly important," said Gerhard Angst, CEO and president of Concept Engineering. "Combining system-level schematic generation capabilities with IP editing and assembly features gives our customers exciting new options to create tools for system exploration and system definition."



 
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