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Date: 19-04-14

Enhanced FPGA software Vivado is 25% faster and support HL synth

Xilinx has released its FPGA programming software latest version Vivado Design Suite 2014.1 offering 25 percent faster runtimes and 5 percent improvement in performance across all devices. Also new to 2014.1 is hardware acceleration of OpenCL kernels, within Vivado High-Level Synthesis (HLS).

UltraFast design methodology video tutorial related to FPGA programming software is viewed 30,000 times and 2,500 of its customers are trained on the UltraFast design methodology, says Xilinx. The updated methodology also includes high-level synthesis, partial reconfiguration, and verification using the Cadence, Mentor Graphics, and Synopsys flows.

The new features as explained by Xilinx includes:

The Vivado Design Suite 2014.1 automates correct-by-construction constraints with the release of a new interactive timing constraint wizard. Intelligence built into the wizard queries the Vivado design database to extract the clocking structure as well as existing constraints, often coming from IP reuse, then guides the user to correctly constrain the rest of the design.

Also introduced with this release is the new Xilinx Tcl Store where the design community can freely publish and share qualified scripts that perform useful functions and improve productivity. The Tcl store is fully accessible within the Vivado Integrated Design Environment and provides an open source repository where designers can make use of scripts that perform functions which extend Vivado Design Suite core capabilities, and tool experts can share code that improves the efficiency of the larger user community. Available today are Tcl applications that provide custom reports, analysis, optimizations, tool flow control, and design changes.

Vivado HLS enables C, C++ and System C specifications to be directly targeted into Xilinx All Programmable devices without the need to manually create RTL. The combination of Vivado IP Integrator and Vivado HLS can significantly reduce development costs—by as much as a factor of 15—versus an RTL approach. With the Vivado Design Suite 2014.1 release, Vivado HLS now offers early access support of OpenCL kernels. OpenCL provides a framework and language for writing kernels that executes across heterogeneous platforms and can now be seamlessly converted to IP running on Xilinx All Programmable devices. Additionally, this release extends Vivado HLS for signal processing applications with a new linear algebra library, enabling rapid IP generation of C/C++ algorithms that require functions such as Cholesky decomposition, singular value decomposition (SVD), QR Factorization, and matrix multiplication.

Vivado Design Suite 2014.1 can be downloaded from www.xilinx.com/download.

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