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Date: 23-04-14

Hardened IEEE 754-compliant floating-point operators in an FPGA

Altera said it has integrated hardened IEEE 754-compliant, floating-point operators in an FPGA, delivering unparalleled levels of DSP performance, designer productivity and logic efficiency. The hardened floating point DSP blocks are integrated in Altera’s 20 nm Arria 10 FPGAs and SoCs – currently shipping – as well as 14 nm Stratix 10 FPGAs and SoCs.

Altera says "Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, Altera’s resource efficient, hardened floating point DSP blocks eliminate nearly all the logic usage required for existing FPGA floating-point computations. This game-changing technology enables Altera to deliver up to 1.5 TeraFLOPs (floating point operations per second) DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices. DSP designers are able to choose either fixed or floating-point modesand the floating point blocks are backwards compatible with existing designs."

Hardened floating-point DSP blocks to help high peformance computing such as big data analytics, seismic modeling for oil and gas industries and financial simulations.

Altera claims its hardened floating-point DSP blocks in Altera FPGAs and SoCs can reduce development time by upwards of 12 months. Designers can translate their DSP designs directly into floating-point hardware, rather than converting their designs to fixed point, as per Altera.

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