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Date: 15-01-14

Cadence claims its C-to-Silicon Compiler saved VLSI design time by 70%

Cadence claims Renesas able to save VLSI design and verification time by 70 percent by utilizing Cadence C-to-Silicon in developing HEVC IP for 4K video processing.

Cadence says Renesas could reduce code size by writing the code in SystemC to create the HEVC IP at a high level of abstraction using which Renesas could do 6x times faster verification compared to register-transfer level (RTL).

“The challenge with developing this HEVC/H.265-compliant IP was to incorporate our proprietary new algorithm, which enables high quality and high compression efficiently,” said Toyokazu Hori, department manager of Platform Base Technology Development Department, Automotive Information System Business Division at Renesas Electronics Corporation. “Deploying the system-level design approach with C-to-Silicon Compiler for the entire design addressed this challenge and we were able to implement the new algorithm very efficiently, achieving a good time-to-market for our advanced new IP.”

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