eASIC and EnSilica have together made available of 16-bit (eSi-1600) and 32-bit (eSi-3200) soft processor cores, based on an EnSilica’s eSi-RISC. eSi-1600 and the eSi-3200 offers flexible configuration options and custom instructions.
The other key features include:
1. Flexible arch supporting number of hardware functions that minimize silicon area.
2. On–chip memory requirements are reduced by inter-mixed 16-bit and 32-bit instructions.
3. Utilizes the industry standard GNU optimizing C/C++ compiler and Eclipse IDE.
4. Debugging through a JTAG interface and hardware breakpoints.
5. Supports instruction and data cache options for both the 16 and 32-bit processor and a MMU, Floating Point Unit and DSP extensions.
“EnSilica are delighted to partner with eASIC and make our IP available through eASIC’s eZ-IP Alliance Program” said Philip Faulkner, Director of Projects at EnSilica. “The combination of our low cost, flexible, high performance processors and the fast design and turnaround time of eASIC’s single mask ASIC devices enables customers to overcome the challenge of software versus hardware partitioning across a wide range of applications. We look forward to continuing to expand the portfolio of IP available under the program,” added Faulkner.
“The eSi-RISC processors make an ideal embedded solution for use on our single mask adaptable ASIC devices,” said Jasbinder Bhoot, vice president, worldwide marketing at eASIC Corporation. “The small footprint coupled with the versatile configurations options provides a highly cost optimized and low power solution.”