Design speed is an important trend today in semiconductor chip design. New versions of most of the EDA software tools offering 10x or even more cut in processing time. Virtual IC and MEMS design software vendor Coventor has announced its MEMS+ 4.0 software suite which allows designs in parallel in the MathWorks MATLAB and Cadence Virtuoso environments. The MEMS+ 4.0 release is capable of exporting models in Verilog-A format and a full 64-bit implementation that allows more accurate modeling of complex MEMS sensors and actuators.
The MEMS+ 4.0 suite helps in designing and verifying precision accelerometers, gyroscopes, microphones and many other types of MEMS. This latest release of the MEMS+ suite extends the scope of the platform by providing a ‘tunable’ accuracy-versus-speed approach for co-designing MEMS and integrated circuits (ICs) and compatibility with more EDA analog/mixed-signal simulation environments.
Using MEMS+ 4.0, MEMS designers can automatically generate and export Reduced Order Models (ROMs) in Verilog-A format for use by VLSI IC designers. These exported models simulate 100X faster than fully non-linear MEMS+ models and are compatible with all commercial analog/mixed-signal circuit simulators that support the industry-standard Verilog-A hardware description language, claims Coventor.
Coventor explain: During model generation, designers can select one or more non-linear input variables; all other input variables are linearized about selected non-linear operating points. This approach is ideally suited to sensor and resonator applications due to their relatively small displacement in comparison to air gaps. In comparison to hand-crafted Verilog-A models, these automatically generated models simulate just as fast while capturing much more behavioral complexity, including multiple degrees of freedom, environmental sensitivities, critical non-linear effects and the influence of packaging on device performance. Equally important, the MEMS+ approach is automated and much less labor intensive, eliminating opportunities for human error and assuring that the models stay in sync with design changes. When IC designers find behavior that requires deeper analysis, they can switch to full MEMS+ models in the Cadence Virtuoso environment for more detailed investigations.
Murata’s ASIC Design Manager Tero Sillanpää says “The Verilog-A Reduced Order Model (ROM) exported from MEMS+ 4.0 captures second order effects not seen in basic hand-crafted models without any compromise in simulation performance. We were able to create a Verilog-A ROM of a complex gyro design in just a few minutes, allowing our ASIC team to work in parallel with the MEMS team on further design iterations. Harmonic simulations in Cadence showed that the model maintained the expected modal frequencies and was stable. Moreover, transient startup simulations were very fast, on the order of 25s CPU time for 1s real time, before front-end electronic components including RC parasitics were added. The robust model exchange between MEMS and ASIC designers enabled by MEMS+ reduces the probability of design error and can help avoid costly redesign iterations needed to address unexpected behavior.”
The MEMS+ 4.0 release also features a full 64-bit implementation of all software components, providing the capacity to handle larger models that more accurately represent device structural details and behavior. This enhancement is particularly relevant for sensor applications due to the increasing structural complexity of state-of-the-art gyro and microphone designs, says Coventor.
“MEMS+ 4.0 further strengthens the only ‘industrial-strength’ platform for MEMS development available today with even greater accuracy, speed, capacity and eco-system compatibility. This latest release is another significant step toward our goal of significantly reducing time-to-market for MEMS products by reducing the need for time-consuming build-and-test cycles,” said Coventor’s CEO Mike Jamiolkowski.
The MEMS+ 4.0 software is shipping now.
For more details visit: http://www.coventor.com