Semiconductor IP vendor Arteris has announced IC-LOGIC GmbH's IO HUB chip is designed by also using Arteris FlexNoC network on chip interconnect IP and C2C chip-to-chip interconnect IP for systems-on-chip (SoCs) from Arteris. IO HUB chip has successfully passed 5,000 tests over a three-month period of time.
IC-LOGIC’s IO HUB is designed provide processors and platforms with range of standard-based I/O interfaces including 3 Gbps SATA (controller and PHY), dual 5 Gbps PCI express (MAC and PHY), Gigabit Ethernet (MAC with AVB and SGMII PHY), and NOR Flash memory serial interface.
IC-LOGIC’s IO HUB chip, which will be deployed into automobiles beginning 2015 is going to be embedded into automotive infotainment systems designed for high-end automobiles.
“IC-LOGIC chose FlexNoC and C2C to create a flexible and high speed communication chip to respond to the increasing demand of high speed connectivity in car infotainment systems,” said Martin Damrau, founder and CEO of IC-LOGIC. “This is yet another ‘first time right’ device by IC-LOGIC’s industry leading team of automotive and industrial semiconductor designers that establishes a new speed record for design to production, delivering a field-hardened chip that will withstand our customers’ rigorous demands.”
“IC-LOGIC’s use of Arteris FlexNoC and C2C interconnect IP has helped reduce design schedules and has demonstrated the benefit of our NoC technology in automotive applications,” said K. Charles Janac, President and CEO of Arteris. “We are excited to partner with IC-LOGIC to support the increasingly complex automotive market.”
IC-LOGIC’s IO HUB enables solutions for the industrial control and automation market segment as well. The chip will be available in volume to be used in industrial settings in Q1 of 2014.
VLSI chip design engineers use Arteris NoC IP to reduce routing congestion by taking advantage of variable link widths and packetization. Arteris says "Whether you are using AMBA AXI3, AXI4, AHB, APB, OCP, PIF or a proprietary protocol, Arteris FlexNoC IP reduces the number of wires by nearly one half, resulting in fewer gates and a more compact chip floor plan."