Analog Devices has released an FPGA-based reference design with software and HDL code for verification of high-speed JESD204B interfaced ADC to FPGA signal integrity. JESD204B is the high-speed serial interface standard by JEDEC for connecting high-speed ADC to chips such as FPGAs and any such high performance ASICs with ADC inputs. The JESD204B Xilinx Transceiver Debug Tool from Analog Devices supports the 312.5 Mbps to 12.5 Gbps JESD204B data converter-to-FPGA serial data interface and Xilinx's 28nm latest 7 series FPGAs and ARM Cortex processor integrated Zynq-7000 All Programmable SoCs. It is available for free to users of ADI's converters and provides an on-chip, 2-D statistical eyescan that helps designers of radar arrays, software-defined radio and other high-speed systems more quickly verify the signal integrity of JESD204B data converter-to-FPGA using gigabit transceivers.
“The Analog Devices JESD204B Xilinx Transceiver Debug Tool provides on-chip eyescanning that augments the test and measurement process by statistically determining signal integrity inside the FPGA,” said Revathi Narayanan, High Speed I/O product manager, Xilinx. “Where other techniques probe the outside of the FPGA package and acquire the signal before it’s been processed by Xilinx’s automatic gain control and equalizer blocks, ADI’s approach yields a more accurate result by utilizing the Xilinx transceiver on-chip eyescan feature to allow developers to monitor the signal integrity and design margin on their JESD204B links inside the FPGA.”
This reference design utilises on-chip silicon in the FPGA itself to collect data. The data is collected directly from the on-chip RX margin analysis feature available in the 7 series IBERT core and manages the data locally inside the FPGA or one of the ARM dual-core Cortex-A9 MPCore processors. The data display is also simpler by displaying the data on an HDMI monitor or over Ethernet to a remote monitoring station. Where as in other similar tools, the signals are measured using hardware outside the FPGA chip, which adds up the cost and also data is transferred back over JTAG to get displayed on a host/development PC in the lab.
ADI’s reference design also measures link robustness using actual JESD204B serial data running to the FPGA. This use of “live” data enables signal fidelity to be monitored even after the design has been deployed in the field, which allows for real-time and predictive maintenance over the life of the product, according to ADI.
Analog Devices offers some of the best ADCs for high speed data conversion. The ADC chips from Analog Devices featuring JESD204 includes AD9250, AD6673, AD9683 and AD6677.