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  Date: 09/10/2013

VLSI design: FastSPICE simulator reduce simulation time from days to hours

Cadence Design Systems has announced a new Fast SPICE simulator which can reduce simulation time from days to hours for complex VLSI design which involves analog and mixed signal. Cadence shared an example of a 600K device power management simulation, it could only take 3.2 hours in the new Spectre XPS simulator compared to 25 hours in the older version of Spectre APS 8 Cores.

The new simulator Spectre XPS features partitioning technology for faster simulation with highest capacity but by using less system memory. This new simulator offers accurate timing measurements and analysis required for deeper nodes such as 14 nm. Cadence claims Spectre XPS is 10 X faster compared to its competitors.

In example provided by Cadence, Spectre XPS took 132 minutes to simulate SRAM with 7.5 million transistors and 25M parasitics. Cadence claims this is 30X faster than other product available in the market.

The key features of Spectre XPS includes:
1. Reduces memory footprint
2. Can run large designs
3. Efficient management of large amount of parasitic
4. Advanced model reduction
5. Feature ready to use netlist, command models, and PDKs
6. Supports analysis from SPICE to FastSPICE
7.Simultaneously solves IR for the real IR impact on timing
8. On the IR impact on timing Spectre XPS reduces margins, greater visibility effect of dynamic power domains.

Tom Beckley, senior vice president custom IC and PCB group, Cadence, who was addressing a gathering of VLSI design engineers at the CDN Live India 2013 event, said they could achieve such a high performance by using powerful algorithms. He stressed the need of such a high-performance tool to speedup analog mixed signal design, which is a common component of SOC design.


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