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Date: 20-09-13

Synopsys' interface IP available for TSMC's 20 nm process

Synopsys said its DesignWare IP portfolio for TSMC 20SoC includes USB, DDR, PCI Express, and MIPI PHY IP Silicon-proven IP portfolio has been designed into multiple customers' SoCs which are ramping to production now.

"TSMC and Synopsys have a long history of collaboration on leading-edge process technology migration, delivering high-quality, proven IP that helps our mutual customers speed their time to volume production," said Suk Lee, TSMC senior director, design infrastructure marketing division. "The availability of Synopsys' high-quality IP portfolio for our 20SoC customers provides a low-risk path to implementing proven IP while reducing SoC power consumption."

"As the leading provider of physical IP with more than 80 test chip tape-outs in 20- and 28-nm, Synopsys is focused on developing IP in the most advanced process nodes to help designers take full advantage of the processes speed and power characteristics while implementing high-quality, proven IP," said John Koeter, vice president of marketing for IP and systems at Synopsys. "By offering a broad portfolio of IP for the 20-nm process, Synopsys enables designers to more easily meet their goals of creating differentiated products with less risk and faster time to volume production, while also reducing the risks associated with moving to the 16-nm FinFET process."

The Synopsys DesignWare USB 2.0 PHY, USB 3.0 PHY, DDR4 multiPHY, PCI Express 2.0 PHY, and MIPI D-PHY for the TSMC 20SoC process are available now.

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