Cadence Design has launched an adapter called SpeedBridge for debugging PCIe 3.0. designs. This adapter is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The SpeedBridge Adapter for PCIe 3.0 helps VLSI designers by providing high-speed interaction with real-world traffic in a pre-silicon environment running production-level software drivers and OS.
The SpeedBridge Adapter is designed for pre-silicon RTL and integration of PCIe-based ASICs and systems-on-chip (SoCs) and allows system emulation under real-world operating conditions. The adapter verifies emulated PCIe 3.0 designs with the actual ASIC or SoC software and hardware, driver and application development, and runs with existing software and software test programs or analyzer.
“Increasingly, designers are faced with a difficult balancing act of managing increasing design complexities and shrinking time-to-market windows,” said Christopher Tice, corporate vice president, Hardware System Verification, System and Software Realization Group at Cadence. “PCIe 3.0 has increased complexity levels including higher data transfer rates (8 gigatransfers per second), backwards compatibility requirements, and different standards for equalization. In order to prevent costly re-spins and time-to-market delays, it is imperative for designers to perform complete system verification under complex real-world conditions with high fidelity full-speed interfaces.”
The Cadence SpeedBridge Adapter for PCIe 3.0 is currently shipping.