Synopsys has made available of its new 28 nm data converter IP. The IP includes ADC, DAC and PLLs. Synopsys claims its 28nm IP offers up to 76% reduction in power consumption and 86% reduction in area, which is important in mobile SOC chips.
Synopsys says " Increasing Synopsys' 12-bit ADCs' performance to 320 megasamples per second (MSPS) enables greater flexibility for system definition in communications applications such as those enabled by LTE and WiFi 802.11ac protocols. "
"As system architects move their designs to advanced process nodes, they are increasingly integrating analog interfaces directly into the main SoC instead of treating these functions as peripherals," said Richard Wawrzyniak, Senior Market Analyst, ASIC and SoC at Semico Research Corporation. "As a result, system architects need analog IP that is available in their required process nodes and meets their systems' area, performance and power supply voltage requirements. Analog IP providers like Synopsys are responding to this need by evolving their analog interfaces, and in particular their implementations of data converters, to take advantage of the high processing speeds and small area offered by advanced process nodes."
These 28nm analog IPs help the design engineers to scale the functions on a SoC uniformly. To increase the conversion rate to 320 MSPS, Synopsys has used successive approximation register (SAR)-based architecture for its 12-bit high-speed ADCs, which offers parallel assembly options for improved area, lower power and architectural scalability. This new architecture is capable of supporting rates beyond 1 gigasample per second (GSPS). When it comes to DAC, new IP supports conversion rates of 600 MSPS, a 50 percent increase in speed over the previous generation, claims Synopsys. These enhancements support oversampling of the signal, which reduces filtering requirements at the output of the DACs and simplifies the circuit design, as per Synopsys.
All the DesignWare IP mentioned above are available immediately.