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Date: 13-07-13

Chip-design EEs can monitor V/I and EM issues while layout is created

Cadence Design Systems is offering in-design electrical verification capability in its Virtuoso Layout Suite for Electrically Aware Design (EAD). VLSI design teams can monitor electrical issues while a layout is created, rather than wait until the layout is completed before verifying that it meets the original design intent. Cadence claims Virtuoso Layout Suite EAD allows engineers to reduce their circuit design cycle by up to 30 percent while optimizing chip size and performance.

Custom IC design engineers can electrically analyze, simulate and verify interconnect decisions in real time, resulting in layout that is electrically correct-by-construction. This real-time visibility lets engineers reduce conservative design practices – or “over-design” – that can negatively impact a chip’s performance and area, suggests Cadence.

The key features Virtuoso Layout Suite EAD according to Cadence includes:
The ability to capture currents and voltages from simulations run in the Virtuoso Analog Design Environment, and pass that electrical information forward into the layout environment
Management capabilities that enable circuit designers to set electrical constraints (like matched capacitance and resistance) and allow layout designers to observe in real-time if these constraints are being met
A built-in interconnect parasitic extraction engine that rapidly evaluates layout as it is created and provides an in-design electrical view for real-time analysis and optimization
Electromigration (EM) analysis that alerts layout engineers to any EM issues that are being created as the layout is drawn
Partial layout re-simulation that helps prevent errors from getting buried deep in a packed layout, thus minimizing re-spins and reducing the need to “over-design”
A greater level of collaboration between circuit designers and layout designers to achieve electrically correct-by-construction layout, regardless of where the team members are located

“Virtuoso Layout Suite EAD represents a big leap forward for automating custom design, enabling layout designers and circuit designers to work together more efficiently and effectively through greater real-time visibility into electrical issues,” said Tom Beckley, senior vice president of R&D, custom IC and simulation, Silicon Realization Group, Cadence. “EAD underscores our commitment to keep evolving our Virtuoso platform to ensure it meets the needs of the countless engineers who rely on it to tackle complex design challenges.”

Cadence Design Systems has also announced that TSMC has expanded collaboration with Cadence on the Virtuoso custom and analog design platform to design and verify its own cutting-edge IP. TSMC is extended its native SKILL-based process design kits (PDKs) portfolio to 16 nanometers. The new PDKs support features within the Virtuoso 12.1 platform, such as auto-alignment, automatic handling of complex rules during abutment, chaining devices, support of color-aware layout, and advanced routing.

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