Synopsys unveiled a new, innovative test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die. The new technology also uses fewer pins and higher-frequency on-chip design-for-test (DFT) circuitry, enabling design teams to test several die in parallel and use the maximum performance of their tester equipment to achieve additional reduction in test time and cost. Embedded in Synopsys' Design Compiler RTL synthesis and TetraMAX ATPG solutions, the new test technology delivers faster test time and higher test quality without adversely impacting design goals and schedules.
"Our initial review of Synopsys' new test technology shows it can achieve up to three times higher compression compared to existing solutions," said Roberto Mattiuzzo, SoC test and diagnosis manager at STMicroelectronics' Central CAD and Design Solutions. "The technology can be deployed on a variety of design styles with any number of test pins and supports high-speed test clocks. It is well aligned with our ever-increasing requirements to lower the cost and raise the quality of test for our silicon products using our current and ready-for-production fabrication process."