Mentor Graphics has teamed with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME (Institute of Microelectronics) silicon photonics process.
OpSIS team has demonstrated a prototype full design implementation and verification flow for the IME silicon photonics process. This flow uses the Mentor Pyxis custom IC design platform for schematic capture and schematic driven layout, along with the Mentor Calibre nmDRC and Calibre nmLVS tools with detailed parameter checking for physical verification of the design. This prototype flow is available for use by design teams who participate in an OpSIS MultiProject Wafer design workshop.
Mentor explains: Within the Pyxis custom IC design platform, the OpSIS PDK currently supports call-back driven photonic PCells that can be quickly assembled using connectivity-driven waveguide routing with radial and adiabatic bends, as well as S-bend support. Design rule checking is done with the Calibre nmDRC tool using out-of-the-box SVRF rules with special considerations for silicon photonic structures, along with the Calibre nmLVS tool for device checking that is similar to other high-volume design flows used in the industry. Tiling and mask preparation is done using Calibre SmartFill in conjunction with the Calibre DESIGNRev tool. Mentor has also partnered with OpSIS to ensure access to design tools so this does not become a barrier to the development of silicon photonics test chips.
“Silicon photonics is becoming an important design enabler, especially for data communications. As this technology finds its way into more and more chips, it is extremely important that traditional EDA providers partner with the companies providing dedicated photonics tools and with foundries supporting silicon photonics. We are very pleased to be part of this collaboration,” said Linda Fosler, director of marketing, Deep Submicron Division, Mentor.