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Date: 21-05-13

Massive parallel processing for chip-design timing closure in days instead of weeks

Cadence Design Systems has introduced the Tempus Timing Signoff Solution, a new static timing analysis and closure tool for faster design closure of SoC class VLSI chip designs.

The new capabilities introduced in the Tempus Timing Signoff Solution include:
The timing engine leverages multi-core processing environment for parallel computing of timing analysis, so that hundreds of millions of instances are analyzed faster and also accurately, as per Cadence. The Tempus Timing Signoff Solution enables broader use of path-based analysis than other solutions.

Cadence says Multi-mode, multi-corner (MMMC) analysis and physically-aware timing closure that leverages multi-threaded and distributed timing analysis and the Tempus Timing Signoff Solution can handle designs containing hundreds of millions of cell instances without compromising accuracy. Initial engagements with customers have shown that the Tempus Timing Signoff Solution can achieve timing closure in days on a design that would have taken several weeks with traditional flows, claims Cadence.

Availability: The Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013. Cadence plans to showcase the tool’s advanced capabilities at DAC, June 3-5, 2013 in Austin, Texas.

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