ARM and Synopsys together in collaboration offering reference designs for implementing ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters as well as the CoreLink CCI-400 cache-coherent interconnect , which three together form muticore SoC based on ARM's big.LITTLE concept. So when time is money for smart phone chip designers, they can go for ready reference such as this to design multi-core SoC.
Synopsys Reference Implementations provide tool scripts, a baseline floorplan, design constraints and documentation to serve as an optimized starting point for implementation. These reference design leverage latest EDA tools from Synopsys which include Galaxy, and IC Compiler. They are configured for TSMC 28HPM process technology with ARM Artisan standard cells, memories and ARM POP technology. Designers may further optimize the scripts for their own design goals, processor configurations, process technologies and libraries. Reference Implementation technology plug-ins for the Synopsys Lynx Design System will enable a full, chip-level production design flow. Synopsys also provides expert professional services to help designers deploy and customize the Reference Implementations to achieve their specific SoC design goals.
The Synopsys Reference Implementation for the Cortex-A7 processor cluster is for a quad-core MPCore configuration, optimized first for energy efficiency, then for maximum speed to provide energy-efficient multi-processing. For high-performance multi-processing within a tight power envelope, the Reference Implementation for the Cortex-A15 processor cluster targets a dual-core configuration, optimized first for performance, then for power. The CCI-400 interconnect implementation is optimized for the combination of these two processor clusters into a big.LITTLE processing system.