Cavium has deployed Jasper’s Architecture Modeling App to specify, model and better verify complex behavior during design and verification of VLSI chip design.
“Our next generation product line uses extremely advanced technology to achieve 100Gbps throughput and rapidly establishing that these blocks function correctly will help speed our time to market and provide our customers with the functionality and performance they require,” said Bruce Fishbein, Vice President of NCD IC Engineering at Cavium. “Jasper’s Architecture Modeling App is helping us further improve our verification processes.”
“Cavium decision to use Jasper’s formal technology for their leading-edge designs is a testament to the power and ease-of-use of our solutions,” said Rajeev Ranjan, Chief Technology Office at Jasper Design Automation. “Our technology has a proven track record with high-end designs. We look forward to partnering closely with Cavium to produce the verification results they require to achieve confidence in their designs.”
The JasperGold Architectural Modeling helps in creating a golden reference model that can be used in verifying the RTL implementation of the protocol; and automates protocol-related property generation and debugging aids.