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New Products

  Date: 07/02/2013

Sixteen 15 Gbps SerDes lanes featured Bandwidth Engine IC operate at 480 Gbps

MoSys has unveiled Bandwidth Engine 2 - Macro with increased access rate and throughput and also featuring offload accelerators for single rate and two rate three color marker (srTCM, trTCM) metering, statistics, and accounting applications.

The Bandwidth Engine 2 family has three purpose-built variants, Burst, Access and Macro designed for high-rel, carrier-grade applications.

MSR820 has sixteen 15 Gbps SerDes lanes to operate at 480 Gbps, providing the host with up to 384 Gbps CRC protected, effective data throughput at 80% overall efficiency. MoSys claims this performance is well beyond the capability of standard memory subsystems and alternative serial interface solutions, while using less than half of the board area, interface pins, and power resulting in substantial system-level cost savings.

MSR820 Bandwidth Engine IC uses fire-forward operations to update records entirely internal to the device, reducing the number of memory bus transactions from six to one, which helps in saving computing time of host required for the update. The MSR820's macros can be saturated using only 8 SerDes lanes, further reducing the power, pincount and host resources. The macro functions can retire entire operations in under 30 nanoseconds (ns), which MoSys claims is far quicker and at substantially lower power than alternative solutions.

"The industry is challenged to provide high-performance line cards that can aggregate hundreds of Gigabytes of bandwidth and deliver ever increasing intelligence," stated John Monson, VP of Marketing at MoSys . "The MSR820 Bandwidth Engine - Macro, delivers up to twelve billion operations per second for onboard or host-based processing, eliminating as many as 6 to 8 transactions with a single command. This industry-leading performance capability, combining memory bandwidth, intelligence features and efficiency improvements, enables networking and compute architects to achieve both increased speed and intelligence for packet or data processing applications."

These ICs feature GigaChip for chip-to-chip communications. They are also compatible with CEI-11G and XFI SerDes for seamless interface with high performance latest FPGAs and standard libraries available from ASIC providers. A complete package of RTL code and tools is provided by MoSys to support the Bandwidth Engine interface.

Availability: Now in volume production

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