Date:29th Nov 2011

Lattice continues to play its role as cost-optimized FPGA solution vendor

While Xilinx and Altera embrace 28nm technology to increase the density of gate elements in FPGAs, Lattice Semiconductor, as usual tries to get maximum benefits out of the established and mature node 65nm. Lattice sees the cost advantage and reliability advantage of 65nm semiconductor fab technology is more valuable than expensive and risky 28nm node. But the Lattice is going to make FPGA chips in 28nm once the cost and reliability of 28m improves. It doesn't want get into 40 nm node at all, due to both economical and technical reasons. Lattice' semiconductor fab service provider for its 65nm chips is Fujitsu.

Lattice has launched the new FPGA family ECP4 with 250K logic elements and has SERDES with 6Gbps speed. Though gate count is less than 28nm FPGAs from Xilinx and Altera, but there is enoungh number to develop FPGA based cards for use in large number of wireless and wireline applications, mainly base stations. Lattice' ECP4 offering is to save the cost and also not rising the power consumption. The more specific applications suggested include Remote Wireless Radio Heads, Distributed Antenna Systems, Cellular Base stations, Ethernet Aggregation, Switching, Routing, Industrial Networking, Video Signal Processing, Video Transmission and Data Center Computing.

The new ECP4 family features increased DSP capability. The DSP capability of FPGA has increased significantly in recent years, forcing DSP application developers to choose FPGA chips instead of DSP chips form vendors such as Texas Instruments and Analog Devices, According to Sidharth Mohanty, General Manager, Lattice India.

Notable features of ECP4 family include:

1. 6Gbps SERDES in low cost wire-bond packages.

2. Sixteen CEI-compliant 6 Gbps SERDES channels with embedded Physical Coding Sub-layer (PCS) blocks PCI Express 2.1, multiple 10 Gigabit Ethernet MAC and Tri-speed Ethernet MACs as well as Serial Rapid I/O (SRIO) 2.1.

3. Digital signal processing (DSP) blocks with 18x18 multipliers, wide ALUs, adder-trees and carry chains for cascadability. Booster logic to 4x multiply the each DSP block compared to ECP3 family. The flexible 18x18 multipliers can be split into 9x9 or combined into 36x36 to perfectly match customers' application requirements.

4. Up to 576 multipliers can be cascaded together to build complex filters for wireless Remote Radio Heads (RRH), MIMO-based RF antenna solutions and video processing applications.

5. 1066 Mbps DDR3 memory interfaces and 1.25 Gbps LVDS I/Os, which can be, provisioned as serial Gigabit Ethernet interfaces.

6. 1.25 Gbps LVDS I/O, with Clock Data Recovery blocks, allows interfacing to high performance ADCs/DACs and implementation of SGMII/GbE links.

7. The CDR functionality on general purpose I/O increases the number of serial I/O available to the designer, allowing smaller FPGAs to be used when a large number of SERDES channels are needed.

Availability: To get samples you got to wait until first half of 2012 and volumes in second half of 2012.