Date: 9th Jun 2011
Verification IP for ARM's AMBA 4 Coherency
Extensions protocol
Cadence Design Systems, Inc. has added a new verification
IP (VIP) for ARM's AMBA 4 Coherency Extensions protocol
(ACE) to its VIP catalog. This is to address the design
trends of using multi core processor in mobile electronic
devices.
The new VIP enables designers to verify the functionality
of multiprocessor ARM Cortex-A15 designs now being deployed
in a variety of mobile applications including consumer tablets
and smart phones. These multiprocessor designs must rely
on cache coherency to effectively execute multiple tasks
simultaneously, a requirement in order to run more powerful
software "apps" with fast response times. The
ACE protocol provides hardware-based cache coherency and
is used in conjunction with ARM Cortex-A15-based multiprocessor
designs. When using the ACE VIP in tandem with Cadence end-to-end
interconnect fabric monitoring, designers have the first
full solution for coherency verification.
"Mobile design complexity has grown to the point that
it requires capabilities previously only found in very high-performance
systems," said Michael Dimelow, Director of Marketing,
Processor Division, ARM. "The ACE protocol provides
the cache coherency required to manage the rising number
of transactions between multiple processors and distributed
memory. This is true for all classes of consumer devices
and, increasingly, in the network and enterprise markets.
ARM has worked closely with EDA partners, such as Cadence,
to ensure that their latest VIP tools are capable of validating
these complex coherent compute systems."
"By working collaboratively with ARM and their leading
Cortex-A15 customers over the last year, we deliver must-have
VIP for verifying systems based on the ACE protocol,"
said Ziv Binyamini, Corporate Vice President of System &
Software Solutions, Research and Development at Cadence.
"This VIP is critically needed to speed the development
and delivery of sophisticated ARM-based mobile devices and
overcome the growing challenges inherent in designing cache-coherent,
multiprocessor systems."
Cadence VIP verifies each master and slave to ensure compliance
with the ACE specification, and works with an interconnect
fabric monitor to ensure coherency of the full SoC, giving
designers confidence that their designs are truly coherent.
Cadence also claims it is the only one, delivering complete
ACE verification solution.
The Cadence ACE verification solution is available now
as part of the broad VIP catalog.
|