40Gb/s System-on-Chip (SoC) for coherent
optical networking from PMC-Sierra
PMC-Sierra, Inc. has announced the 40Gb/s System-on-Chip
(SoC) solution for coherent optical networking. PMC-Sierra
claims the PM6373 POLO 40G doubles line card density and
reduces power consumption by more than 50 percent when compared
to 40G non-coherent network deployments. PMC-Sierra says
its unique combination of high-performance mixed-signal,
digital signal processing (DSP), analogue to digital convertor
(ADC), OTN framing and Swizzle Forward Error Correction
(FEC) SoC architecture digitally compensates for optical
impairments and improves optical performance by more than
2dB for an additional 25 percent fiber reach extension,
which dramatically lowers the cost of transmission.
"Carriers are choosing coherent deployments because
it is the most effective technology to increase fiber transmission
rates and build all-optical networks," said Andrew
Schmitt, directing analyst of Optical at Infonetics Research.
"Coherent technology is one of the fundamental technologies
of what I call the Optical Reboot: the optical network architecture
transformation that will take place this decade."
PMC-Sierra's POLO 40G eliminates widely deployed optical
equipment such as dispersion compensation management (DCM),
dispersion compensated fiber (DCF), and hands-on operational
cost of tuning and managing this equipment so that OEM line
cards can transit from today's two- or three-slot implementations
to single-slot. Line card tuneable dispersion compensators
(TCMs) are no longer required.
"With the explosion of bandwidth demand driving the
need to upgrade existing metro, regional and longhaul fiber
infrastructures to 40Gb/s and beyond, POLO 40G will be a
key enabler to make the optical buildout a reality,"
said Daryn Lau, vice president and general manager of PMC-Sierra's
Communication Products Division. "PMC-Sierra has significant
experience in delivering innovative products to enable evolving
Carrier network requirements. Our POLO 40G is uniquely positioned
to provide the combination of bandwidth per unit, power
and cost when compared to existing multi-slot coherent solutions
even in cost-sensitive Carrier Ethernet service point-to-point
and metro deployments."
POLO 40G is a single chip CMOS coherent DP-(D)QPSK transmission
transceiver that delivers the full set of compensation capabilities,
including chromatic dispersion (CD), polarization mode dispersion
(PMD), second order PMD (SOP), and high-rate polarization
tracking, among others. The platform provides an SFI 5.1
client interface and a fully OIF-compliant line side DP-(D)QPSK
interface that seamlessly integrate into MSA optical modules
and onto a line card with next-generation CFP2 optical modules.
POLO 40G also incorporates flash ADC technology with background
calibration to maintain operating performance in demanding
Carrier environments.
Full Bit Transparent Operation: Supports all FEC overhead
rates between seven percent and 20 percent and backward
compatible with legacy 40Gb/s coherent solutions.
Blind Equalization and Interoperability: Utilizes ITU standard
OTL3.4 encoding/decoding for polarization resolve and ITU
standard G.709 FEC to drive broad industry interoperability.
Extended Reach with High Gain 18.8 Percent FEC Option: +2dB
additional OSNR margin provides an additional 25 percent
reach extension over all other seven percent enhanced FEC
implementations.
Increased Spectral Efficiency: 40Gb/s DP-(D)QPSK is ready
made for future 25GHz ITU grid spacing that doubles spectral
efficiency from 0.8Bit/s/Hz to 1.6Bit/s/Hz.
White Paper from PMC-Sierra titled "The Era of Coherent
Optical Networking" provides an overview of coherent
optical technology and the critical power, cost, and optical
challenges it solves to enable Carriers to deliver a tidal
wave of high-capacity services with much lower capital and
operational costs. The paper is available for download at
www.pmc-sierra.com/wireline (registration required).
Availability: PMC-Sierra's PM6373 POLO 40G will
sample later this year for sponsor customers. The device
is implemented in 40nm CMOS technology and packaged in a
480-pin 23mm x 23mm FCBGA package.