New IP cores from Xilinx meets AMBA 4 specifications

Xilinx has released the ISE Design Suite 12.3, IP cores that meet the AMBA 4 AXI4 specification for interconnecting functional blocks in System-on-Chip (SoC) design. These IP cores have a PlanAhead Design and Analysis cockpit, and Intelligent Clock Gating support, enabling reduced power consumption in Spartan-6 FPGA designs.

"Xilinx is the first to standardize on the AMBA 4 specification as part of our interconnect strategy to support Plug-and-Play FPGA design. SoC designers who have large investments in AMBA AXI3 and AXI4 interface IP have good reason to use Xilinx programmable platforms compared to alternative FPGA and ASIC solutions," said Vin Ratford, Senior Vice President, Worldwide Marketing at Xilinx. "The flexibility inherent in the AXI4 interconnect enables it to be tailored for performance and area all while making it easier for customers to integrate IP from different domains and IP providers. It also enables ASIC designers to migrate pre-existing designs and IP to Xilinx FPGAs."

The deployment of the AMBA 4 AXI4 specification will enable support for Plug-and-Play FPGA design. The ISE Design Suite 12.3 includes enhancements to the CORE Generator tool that provides access to highly parameterized IP as well as the Xilinx Platform Studio and System Generator tools. Xilinx's adoption of the AMBA protocol provides access to ASIC verification methodologies and existing AMBA protocol-based IP.

"The increases in complexity and scale for new designs means that communication and interconnect are critical to system performance," said Michael Dimelow, director of marketing, Processor Division at ARM. "The open nature of the AMBA standard delivers tremendous benefits to system designers by expanding the variety of IP available for implementation in SoC's and FPGAs, and thus accelerating time to market."

"Mercury's commitment to standards and industry leverage has led us to conform to AXI4 because of its broad ecosystem support, time-to-market benefits and alignment to Xilinx's product roadmap," said Charlie Frazer, Director of Silicon IP Engineering at Mercury Computer Systems

"Cadence has long provided industry-leading AMBA verification solutions for SoC Realization, and our support of AXI4 in collaboration with Xilinx will be welcomed news for SoC designers who rely on Cadence's advanced verification IP and enterprise verification technologies to target their designs to FPGA for prototyping or production," said Michal Siwinski product management group director for System and SoC Realization at Cadence. "Our collaboration with Xilinx means integrators now have bus functional models they can use with any tool suite to model and verify their designs more easily."

Price: starting at US$2,995

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