Date: 26th July 2010

Radiation hardened FPGA from Xilinx enable last minute design changes

Xilinx has released the Virtex-5QV FPGA, an high-densit, rad-hard reconfigurable FPGA for applications ranging from low earth-orbiting satellites to systems supporting inter-planetary missions. This FPGA has integration capabilities for complex systems that would otherwise require rad-hard ASIC devices. The combination of rad-hard and re-configurability enables minimal-cost, last-minute design changes and even redesigns after launch.

"For over 20 years Xilinx has been enabling space systems designs with our rad-tolerant FPGA platforms and Single Event Effects mitigation design methodologies," said Amit Dhir, senior director, Aerospace/Defense & High-Performance Computing Business at Xilinx. "With the Virtex-5QV FPGA we are enabling new and unprecedented applications in FPGAs, bringing to market a platform that utilizes new rad-hard by design technologies paramount in providing radiation hardness, higher density, higher levels of performance and simpler mitigation schemes compared to previous Xilinx devices."

The Virtex-5QV device enables delivering programmable solutions that help developers avoid the high cost of ASIC development and still meet the performance and integration requirements specific to their markets. The Virtex-5QV FPGA is suitable for space systems thus enhancing applications such as video display, communications, radar, encryption, packet processing and control.

"The radiation hardened Xilinx Virtex-5 FPGA represents the biggest step ever taken in performance and affordability for space electronics. Our Air Force satellite developers will be able to do more on-board processing using less power than ever before. And, the flexibility of the Virtex-5QV FPGA means that satellite development schedules will be shortened, saving even more money," said Dr. David A. Hardy, associate director, Space Technology, Space Vehicles Directorate, Air Force Research Laboratory.

The radiation-hardened version of the commercial Xilinx Virtex-5 FPGA was developed under sponsorship by the United States Air Force, Air Force Research Laboratory (AFRL), 3550 Aberdeen Avenue SE, Kirtland AFB, NM 87117-5776.

According to Dave Jungkind, director, Business Development at SEAKR Engineering, Inc., "SEAKR has several programs that are base-lining Xilinx devices, but what the new Virtex rad-hard FPGAs will bring is a step function improvement in size, weight, power and performance. SEAKR is investing heavily to bring this game-changing capability to the aerospace market."

The Virtex-5QV FPGAs provide protection against Single-Event-Upset (SEU), Immunity to Single-Event Latchup (SEL), high tolerance to Total Ionizing Dose (TID), as well as data path protection from Single-Event Transients (SET).

The new devices are built on the second-generation ASMBL column-based architecture of the Virtex-5 family with support in Xilinx's ISE Design Suite. Virtex-5QV devices integrate hard-IP system level blocks, such as flexible 36-Kbit/18-Kbit block RAM/FIFOs, second generation 25x18 DSP slices, power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, and PCI Express compliant integrated Endpoint blocks.

The Virtex-5QV device offers 130,000 logic cells, 320 DSP Slices supporting fixed and floating point operations, and 836 user I/Os programmable to more than 30 different standards for applications and ease of interfacing to a wide variety of system components.

The Virtex-5QV family also provides high-speed connectivity solution for space with 18 channels of 3Gbps Multi-gigabit Serial Transceivers for chip-to-chip, board-to-board and box-to-box communication.

Availability:
The Virtex-5QV device will be sampling in the current quarter with general production availability planned for first half calendar year 2011.