Cadence and ARM to jointly develop an
optimized system realization solution for ARM processors
Cadence is broadening its existing collaboration with ARM
to develop an optimized System Realization solution for
ARM processors that will enable an end-to-end flow including
a full set of interoperable tools, ARM processor and physical
IP, services and methodology from embedded Linux to GDSII.
Cadence will also provide a full complement of tutorials
and education materials including two methodology reference
books and extend their ecosystem of service, methodology
and training providers.
"As software complexity continues to escalate driving
system costs up, industry leaders need to join forces to
provide proven and cost effective end-to-end design solutions,"
said Mike Muller, ARM, chief technology officer. "Only
a comprehensive approach from application software through
silicon can successfully address the challenges facing our
design community. This collaboration with Cadence will not
only address the rapidly rising cost of integrated hardware
and software system development, but will also accelerate
time-to-market for next-generation consumer products."
To deliver this solution, Cadence will take the following
actions:
1. Support embedded software optimized for ARM processor-based
devices in the company's recently announced
IP stacks.
2. Enhance the interoperability of ARM tools and IP including
ARM DS-5 and RealView Development Suite,
Fast Models, and VSTREAM transactor with Cadence Virtualization
technologies.
3. Expand its existing collaboration on AMBA IP-VIP pairs
and interconnect fabric, and reference methodologies
for design, verification, and implementation
"As our business is expanding into the mobile market
segment, ARM processor-based designs are becoming a larger
part of our development," said Narendra Konda, director,
Hardware Engineering at NVIDIA. "The Cadence/ARM collaboration
provides the right approach for the industry by addressing
application-driven flow. This integrated flow will help
us to improve our system validation process which is one
of the most critical components for our success."
Cadence also plans to extend its System Realization ecosystem
through new collaborations with service, methodology and
training providers that will help accelerate customers'
deployments of system-level solutions. The new companies
include Australian Semiconductor Technology Company (ASTC),
Chubu Toshiba Engineering Corp, CircuitSutra, CM Engineering
Co. Ltd., HDLAB Inc., Nippon Systemware Co. Ltd., and Toshiba
Information Systems (Japan). The full list of members can
be found at www.cadence.com/alliances/system_realization.
"Cadence continues to build our System Realization
solution through collaboration with others and delivery
of new methodologies," said John Bruggeman, chief marketing
officer, Cadence. "The Cadence and ARM solution will
combine industry leading IP to help break down the cost
and development barriers that are preventing consumer devices
from achieving breakaway market success. ARM IP is prevalent
in current and future consumer devices, and the jointly
developed solution will unleash new, compelling innovation."
To further help customers achieve efficient, cost-effective
adoption of System Realization aspects, Cadence has developed
the industry's first transaction-level modeling (TLM) design
and verification methodology, available to the industry
in its newly published book titled, "TLM-driven Design
and Verification Methodology." To accelerate SoC integration
and verification based on the recently standardized Universal
Verification Methodology (UVM), Cadence also has released
another new book titled, "A Practical Guide to Adopting
the Universal Verification Methodology (UVM)." Together,
they provide a pragmatic set of best practices to help accelerate
solution deployments.
For more information visit: www.cadence.com.
