USB 3.0 integrated PHY and controller IP for SoCs

Gennum's Snowbush IP group has developed the industry's first available integrated USB3.0 SuperSpeed PHY and controller IP core solutions for system-on-a-chip (SoC) and system companies.

"Our Snowbush IP group has delivered silicon-proven cores based on the industry's most pervasive high-speed interconnect standards, such as PCI Express Gen2 and SATA Gen2, enabling many high-profile semiconductor suppliers and OEMs to get to market first with products based on these standards," said Ewald Liess, General Manager of the Snowbush IP group for Gennum. "Our extensive experience at data rates of 5 Gb/s and above, combined with over 200 million products that have been shipped with our IP, allow us to deliver high-speed serial interface IP that is high yielding, and optimized for the performance, power, size and cost of our customers' target applications. Moreover, our extensive background in developing, licensing and supporting IP integration lowers the risk and time-to-market associated with complex SoC design."

USB 3.0, which is also called as SuperSpeed USB can transfer data at 5 Gigabits per second (Gb/s) in each direction.

"SuperSpeed USB will be key in several applications, including PCs, external storage, digital camcorders and digital still cameras. SuperSpeed USB products should begin to hit the market in the next 12 to 18 months, with growth rates exceeding 100 percent annually between 2009 and 2012," said Brian O'Rourke, principal analyst, digital entertainment, at market research firm In-Stat. "The availability of IP that will speed the design of SuperSpeed USB products will have a tremendous impact on that growth, as well as provide a market advantage as manufacturers are able to quickly bring new and differentiated products to the industry."

Snowbush IP Core Enables SuperSpeed USB. The integrated Snowbush device PHY and controller solution satisfies all the critical specifications of SuperSpeed USB.

The new IP block employs below techniques for better performance, reduced jitter and maximum noise immunity, including:
1. A proprietary dual-loop hybrid clock-and-data recovery (CDR) architecture which recovers the clock with less jitter
2. A coupled ring oscillator VCO design for reduced jitter
3. Internal voltage and current regulation for sensitive circuits
4. Fully differential circuitry and clock signaling
5. Extensive use of guard rings within the macro

The Snowbush integrated PHY and controller IP is available immediately for licensing, and is provided for manufacture in 90-, 65- and 45- nanometer processes.