New dual-core SoC with image recognition function for automotives

Renesas Technology has announced the SH7776 (SH-Navi3), a dual-core system-on-chip (SoC) device with on-chip enhanced graphics functions and a high-performance image recognition processing function for the car information terminals that evolved from car navigation systems. The SH7776 (SH-Navi3) integrates two CPU cores on a single chip with a processing performance of 1,920 million instructions per second (MIPS).
Sample shipments will begin in April 2009 in Japan.

The new SH7776 dual-core SoC device serves the performance and functional demands of a "next-generation car information center." It enables display of colorful and realistic 3-D graphics use of a multimedia and information communication as well as navigations, display of 2-D/3-D graphics use of a graphical user interface (GUI) for enhanced user-friendliness, and image recognition for functions such as lane detection and preceding vehicle tracking. In addition, functions for strengthening the system reliability of the dual-core architecture are embedded on the chip.

The key features of the SH7776 (SH-Navi3) are,

1. The SH7776 (SH-Navi3) integrates dual Renesas Technology SH-4A high-performance 32-bit CPU      cores.
2. 3-D graphics engine for colorful and more realistic 3-D images as well as 2-D and 3-D graphics      processor
3. Industry's first dual-core SoC product for car navigation systems with on-chip image recognition     processing function
4. DDR3-SDRAM memory interface and PCI Express interface for ultra-high-speed data transfer.
5. Integrates on-chip peripheral modules required by car navigation systems, including a serial-ATA     interface, a USB 2.0 Host/Function interface, a TS interface for receiving terrestrial digital TV     broadcasts, and a GPS *7 baseband processing module.
6. The dual-core architecture supports the following two types of processing, providing flexibility to meet     a wide range of customer requirements.
    A. Symmetric multiprocessing (SMP), in which the operations of a single program running under a         single OS are divided between two CPU cores for parallel processing, is supported.
    B. Asymmetric multiprocessing (AMP), in which different OSes (or multiple instances of the same          OS)     and completely different programs run on each of the CPU cores, is supported.

Package: 653-pin BGA (25 mm x 25 mm).