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Date: 26-01-09

Pair of free RF design EDA software tools from Anlog Devices

Analog Devices has announced the availability of two free EDA software tools for RF system design.

The ADIsimRF design tool calculates a variety of parameters within an RF system including cascaded gain, noise figure, IP3, P1dB, and total power consumption. The calculator can be easily switched between transmit mode and receive mode where calculations and data entry are input referred. Designers can vary the number of stages up to a maximum of 15, and additional stages can be inserted at any point in the signal chain. In addition, designers can temporarily disable individual stages, clear their data, or remove them completely. ADIsimRF also contains embedded data from many of ADI's RF ICs. A designer can easily access this data using pull-down menus, thereby eliminating tedious data entry. The tool also includes device tables to assist in component selection.
For further details visit: http://www.analog.com/pr/adisimrf

The new ADIsimPLL Version 3.1 design tool eliminates time-consuming iterations from the Phase Locked Loop (PLL)/synthesizer development process. ADI has optimized its ADF4xxx synthesizers for applications such as wireless base stations, LAN, mobile handsets and PDAs, broadband wireless access, industrial, instrumentation and test equipment, satellite, sonar, and CATV. Analog Devices' ADIsimPLL Version 3.1 design tool offers support for the company's latest PLL synthesizers, including ADF4350, ADF9010, ADF4360-9, and the ADF4157. In addition, the design tool includes a new simulation capability for fractional-N spurious estimation. This feature provides an initial assessment of the amplitude and offset of fractional-N spurs. It also allows the user to adjust parameters that set the spur amplitude in response to various loop filter selections, enabling RF designers to incorporate their measurements to further refine the effects of spurs within their system. ADIsimPLL version 3.1 offers an enhanced library of components, including new VCO libraries and improvements to existing component libraries. It also features new loop filter topologies and improvements to the chip-selection algorithm and the power-up simulation.

For further details visit: http://www.analog.com/pr/adisimpll

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