ispLEVER 7.2 FPGA design tool suite with advanced route algorithms

Lattice Semiconductor announced Version 7.2 of its ispLEVER FPGA design tool suite with advanced place and route algorithms that deliver higher performance results in as much as 30% less time. The ispLEVER 7.2 software also supports Lattice's "clock boosting" flow for the LatticeECP2 and LatticeECP2M FPGA families. Clock boosting can result in up to a 5% increase in FMax with no additional user input.

In addition to performance improvements, ispLEVER Version 7.2 continues to improve designers' productivity with additional control, analysis and workflow enhancements, and includes the latest release of Synopsys' Synplify Pro advanced FPGA synthesis solution.

Using the new place and route techniques, ispLEVER software can now analyze a design and automatically choose the most appropriate algorithm for the design's topology. The ispLEVER 7.2-tool suite gives more user control over the use of Global Set/Reset routing. This can result in improved routability and performance for designs with demanding routing requirements.

The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more.

Availability: version 7.2 for Windows, Linux and UNIX users is available
immediately without charge for customers with active design tool maintenance.

Pricing: The full ispLEVER design tool suite is priced at $1295 for the Windows version.

For more information, visit www.latticesemi.com