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Date: 29-01-10

Synthesizable, 32-bit LEON processor based on SPARC V8 architecture

Aeroflex Gaisler AB, has extended its LEON processor portfolio with the introduction of LEON4, a synthesizable VHDL model of a 32-bit processor core based on the SPARC V8 architecture. The new LEON4 processor is suitable for embedded, consumer, and industrial applications.

The LEON4 is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Aeroflex Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL, MAC and DIV instructions and an optional IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU).

The key features of the LEON4 processor are,

SPARC V8 instruction set with V8e extensions
Advanced 7-stage pipeline, with branch prediction
64-bit single-clock load/store operation
64-bit 4-port register file
Separate instruction and data L1 cache (Harvard architecture) with snooping
Configurable caches L1: 1 - 4 sets, 1 - 256 kbytes/set. Random, LRR or LRU replacement
Local instruction and data scratch pad RAM
Configurable L2 cache with 256-bit internal, 1-4 ways
SPARC Reference MMU (SRMMU) with configurable TLB
Advanced on-chip debug support with instruction and data trace buffer, and performance counter
Symmetric Multi-processor support (SMP)
Power-down mode and clock gating
Robust and fully synchronous single-edge clock design
Up to 150 MHz in FPGA and 1500 MHz on 32 nm ASIC technologies
Extensively configurable
Large range of software tools: compilers, kernels, simulators and debug monitors


"We are pleased with the performance of this next generation processor. The power and size optimized LEON4 is fully software compatible with previous LEON processors, yet with a performance increase of up to 50% at the same clock frequency. LEON4 implements single-cycle load/store instructions, as well as static branch prediction. The register file and internal load/store data paths have been extended to 64-bits, while the data cache and bus interface can be either 64- or 128-bit wide. An optional Level-2 (L2) cache has also been added to the architecture, further improving performance on data intensive and multi-core applications. The LEON4 processor delivers up to 1.7 DMIPS per MHz or 0.35 SPECINT2000/MHz.," said Jiri Gaisler, CTO and Founder of Aeroflex Gaisler.

For more details visit www.aeroflex.com/Gaisler

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