PCI Express 3.0 protocol analyzer and
new Mid-bus probe from LeCroy
LeCroy has released the Summit T3-16, a new PCI Express
3.0 protocol analyzer that captures, decodes and analyzes
PCI Express bus traffic at data rates up to 8 GT/s per lane
on bus widths up to 16 lane, with an effective data transfer
rate of 2X the previous PCIe 2.0 specification (5 GT/s).
The Summit T3-16 is targeting high-speed PCI Express I/O-based
applications.
In addition to the Summit T3-16, LeCroy's PCI Express protocol
test family includes the Edge T1-4 for PCIe 1.0 with lane
widths up to x4, the PETracer ML Analyzer and Exerciser
for PCIe 1.1 with lane widths up to x8, and the Summit T2-16
Analyzer and Summit Z2-16 Exerciser for PCIe 2.0 with lane
widths up to x16.
"LeCroy is in a unique position to offer the only
protocol analyzer to early adopters of PCIe 3.0 technology,"
said John Wiedemeier, Product Marketing Manager of LeCroy's
Interconnect Communications Group. "The Summit T3-16
protocol analyzer not only supports a 8 GT/s recording speed
with the industry's most advanced software tools, but also
supports two probing methods that can tap the high speeds
of PCI Express 3.0. PCIe 3.0 achieves an effective data
transfers rate of 2X the previous specification through
the combination on an increased data rate and significant
reduction on overhead during data transfer."
LeCroy has also introduced a new mid-bus probe for the
Summit T3-16 Protocol Analyzer, supporting the PCI Express
3.0 specification (8 GT/s data rates). The mid-bus probe
can be connected to systems that utilize the Intel mid-bus
probe footprint specification.
Mid-bus probes are used to probe embedded bus signals (e.g.,
for serial data buses that run between chips on a single
circuit board), or simply as a convenient means to access
bus signals with a probe connector. The probe is easily
attached to an anchor connector mounted on top of a mid-bus
footprint that is laid out on the test target system board.
The LeCroy mid-bus probe uses a full-size connector that
supports PCIe x8 lanes at 8 GT/s. Two mid-bus probes can
be connected to a Summit T3-16 Analyzer and will support
x16 lane widths. These probes can be used in conjunction
with the unique lane swizzling feature on the Summit T3-16
Analyzer, which allows probe signals to be reorganized logically,
to give developers flexibility in PCB layout.
"Mid-bus probes are a key tool for early developers
of PCIe 3.0 systems," said John Wiedemeier, Product
Marketing Manager, LeCroy. "Enabling bus probing allows
for rapid development of new system designs. Our customers
have come to depend on the high quality probing solutions
from LeCroy to insure successful power-on schedules for
the next generation of high performance I/O."
Availability:
Summit T3-16 and mid-bus probe: Now
For more details visit www.lecroy.com
