Low-resistance Cu interconnect tech with partially-thickened local structure

NEC Electronics has announced the development of its new low-resistance copper (Cu)-interconnect with partially-thickened local (PTL) structure.

The new PTL interconnect technology addresses the resistivity increase of Cu-interconnects, which degrades the radio frequency (RF) performance of analog transistors. By implementing the new developed PTL interconnect technology into the 40-nanometer (nm) node low-power CMOS LSIs, NEC Electronics achieved better RF performance suitable for wireless communication technologies, including long-term evolution (LTE) and WiMAX specifications.

The key features of the new low-resistance Cu interconnects technology are,

Without any change in the in-plain scaling, an low-resistance Cu interconnect is formed by selectively thickening specific parts of a Cu interconnect where low-resistance is strongly required. By applying full low-k (FLK) dielectric materials in addition to the new PTL technology, a Cu interconnect can reduce parasitic capacitance and yet still achieve low resistance.
By implementing the PLT-interconnect structure to connect the gate-electrode as an input ports of analog transistors for RF signals, reducing input resistance of the Cu interconnect by 50 percent.
The new low-cost fabrication process suppressing micro-loading effect developed to adopt both the new slit-shaped PTL-interconnect and the columnar-shaped Cu contact-plugs, required to connect the CMOS transistors and the Cu interconnects.

NEC Electronics' flexible-layout PTL interconnect technology reduces contact resistance and local-interconnect resistance and provides analog interface performance suitable for high-frequency and broadband CMOS wireless terminals, embedded DRAMs and multi-core SoCs, while preserving low power consumption.

For more details visit www.necel.com