Functional verification tool from Real Intent address X-handling issues of VLSI designs

VLSI EDA tool vendor Real Intent has launched new functional verification product family called Ascent addressing the X-handling issues of chip design.

The X(unknown)-logic sources from components like RAM and others pose a challenge in design verification, which includes masking real design errors and causing RTL-to-netlist simulation mismatches. Designer spend more time to avoid X ambiguity in case of both X-pessimistic (leading to unnecessary unknown values) and X-optimistic (resulting in known values when they should have been unknown).

This new Real Intent tool detects explicit and implicit X sources and uses structured and formal analysis to prove X-optimism safe designs. Ascent SimPortal can augment simulation to detect X-excitation, control X-pessimism, and eliminate X-optimism without loss of efficiency. It detects and debugs design errors and RTL/netlist simulation mismatches.

"Real Intent, as the leader in providing automatic functional verification solution for ASIC and FPGA designs, has been approached by many customers with issues related to X-handling in their designs," commented Prakash Narain, President and CEO at Real Intent. "Ascent PBV meets the needs and rises to the challenges by using multiple innovative technologies to ensure X-robust designs. We deliver verification confidence to our customers by turning their verification unknowns into the known."