RapidIO 2.1 spec IP core from Altera for FPGA based system developers

Altera has made available RapidIO IP core supporting the RapidIO 2.1 specification. The RapidIO IP core from Altera supports up to four lanes at 5.0 GBaud per lane supporting the bandwidth and reliability requirements of the wireless and military markets. The IP core is optimized for Altera's 40-nm Stratix IV GX and Stratix IV GT FPGAs and HardCopy IV GX ASICs.

The RapidIO 2.1 specs enhance the speed of communication to 20 GBaud to increase data throughput in systems such as wireless basestations, defense systems and DSP farms. The other 2.1 enhancements include mode to facilitate short 5Gbaud links without DFE and with the IDLE1 control symbol and increased robustness of the IDLE2 operation.

Altera's Serial RapidIO solution are backward compatible to the RapidIO 1.3 specification, reference designs, application notes, testbenches, and interoperability reports with digital signal processor and switch vendors. The Serial RapidIO IP core has been qualified against the RapidIO Trade Association's bus functional model.

"Serial RapidIO is a popular interface for many of our wireless and military customers who put the utmost importance on system bandwidth and reliability," said Luanne Schirrmeister, senior director of component product marketing at Altera. "Combining the industry's first Serial RapidIO IP core supporting the 2.1 specification with Altera's industry-leading FPGA and transceiver technology solidly positions us to address our customer's most important system requirements, including performance, reliability and scalability."

Availability: Now

For more details visit www.altera.com