Xilinx' IBIS-AMI FPGA transceiver models save simulation time

Xilinx has made available IBIS-AMI models for FPGA transceivers to reduce simulation time from hours to minutes.

Xilinx says, By using Xilinx's IBIS-AMI models and SiSoft's Quantum Channel Designer software, systems designers can experiment with different combinations of channel lengths, connectors, via designs and transmit / receive equalization to quickly determine which configurations provide adequate operating margin and which don't. Pre- and post-layout simulation with Quantum Channel Designer allows designers to validate designs and reduce time to market while increasing confidence in their design's reliability and manufacturability.

"Our experience helping customers implement the industry's first 100Gbps designs has taught us that HSPICE simulations of these wide datapaths can take hours to achieve a result," said Senior Director of the Xilinx SERDES Technology Group, David Demarinis. "As a result, we are pleased to announce the public availability of the first IBIS-AMI models in the FPGA industry to allow customers 100x faster simulation times."

Xilinx IBIS-AMI models can be downloaded at http://www.xilinx.com/support/download/virtex5ibisami.htm

Why IBIS-AMI?
Next generation communications, networking, and consumer electronics products are replacing high-speed parallel interfaces with multi-gigabit serial links as the primary means of moving data within a system. Conventional signal integrity and timing analysis (e.g. HSPICE) won't work for these links, which require analyzing millions of bits worth of behavior to reliably determine how jitter, noise and crosstalk affect link operating margins.

The IBIS-AMI (I/O Buffer Information Specification - Algorithmic Modeling Interface) modeling specification enables standardized, interoperable simulation of SerDes PHYs at the high levels of simulation performance and accuracy needed to correctly predict the behavior of serial links. This webinar highlights how IBIS-AMI based simulation will enable you to increase design reliability while reducing engineering design time.

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