40nm PCI Express 2.0 PHY from MoSys

MoSys has made available a 40nm PCI Express 2.0 PHY that complies with the PIPE 2.0 specification and provides the physical layer (PHY) interface that connects to PCI Express 2.0 controllers.

"The PCI Express standard, provided by PCI-SIG, is based on a very complex and technical specification requiring best-in-class IP," said David Lin, Vice President of Marketing at Denali Software. "MoSys' PCI Express 2.0 PHY, together with our Databahn PCIe controller IP and PureSpec PCIe Verification IP, extends our ability to offer high-quality end-to-end interface solutions to meet the needs of our mutual 40nm customers."

"There is strong demand for high-quality, silicon proven SerDes interface IP at 40nm," said David DeMaria, Vice President of Business Operations for MoSys. "The availability of our PCI Express 2.0 PHY and its seamless interoperability with Denali's PCI Express controllers ensures speedy time to market for our customers' chip designs."

"The high speed interface requirements for our ASICs are demanding," said Anil Mankar, Senior Vice President of VLSI Engineering for Mindspeed Technologies. "We selected the PCI Express 2.0 solution from MoSys because it precisely met our requirements."
"Customers of our ASIC designs have stringent requirements for high speed PHYs," said Amal Bommireddy, Vice President of Engineering at AppliedMicro. "MoSys' PCI Express PHYs have helped our ASIC design teams exceed those requirements."

MoSys' PIPE 2.0 compliant PCI Express 2.0 PHY is available now using 40nm and 65nm processes. The PHY is available for both wirebond and flipchip packages.

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