8.0 GT/s PCI Express 3.0 interface IP for system-on-chip (SoC) from Synopsys

Synopsys has launched PCI Express 3.0 interface IP for system-on-chips (SoCs) used in high-performance enterprise computing applications.

Built on the DesignWare IP for PCI Express 2.0 and 1.x architecture, the DesignWare IP for PCI Express 3.0 consists of digital controllers, PHY and verification IP. PCI Express 3.0 is the next generation of the PCI Express I/O standard, which is currently under development within the PCI Special Interest Group (PCI-SIG).

"Synopsys has been an active member of the PCI-SIG since 2003, participating in the working groups and contributing to the evolution of the PCI Express specification," said Al Yanes, PCI-SIG chairman and president. "As a provider of PCI Express IP, Synopsys supports the latest version of the PCI Express 3.0 specification to help facilitate the early adoption of PCI Express 3.0 into the enterprise computing market segment."

DesignWare IP for PCI Express is used in Agilent's Protocol Test Cards (PTC), a required Gold Test at the PCI-SIG compliance workshops. The DesignWare IP has passed Agilent's Jammer in-line error injection testing, which injects disruptive test scenarios to test the reliability and robustness of the PCI Express design.

"Neterion is at the forefront of developing high-performance products for the enterprise computing market and PCI Express is a key technology for our product roadmap," said Dennis Shwed, vice president of hardware development at Neterion. "We have been very successful in incorporating the Synopsys DesignWare IP for PCI Express in our current products and are excited to see Synopsys aggressively embrace PCI Express 3.0. This is exactly what we have come to expect from an industry leader like Synopsys."

The DesignWare digital controllers for PCI Express 3.0 implement the same interfaces as PCI Express 2.0, allowing customers to quickly upgrade to PCI Express 3.0. For the physical layer, Synopsys is developing a PHY architecture specifically optimized for PCI Express 3.0 with high-performance margins to allow the PHY to achieve the final PCI Express 3.0 specifications in areas such as jitter, margin, and receive sensitivity. In addition, the advanced built-in diagnostic capabilities and ATE test vectors enable at-speed product testing of the DesignWare PHY IP for PCI Express 3.0 and on-chip visibility into the actual link performance. Complementing the digital controllers and PHY is the DesignWare Verification IP for PCI Express 3.0, which supports directed testing and constrained random methodologies defined in the Verification Methodology Manual (VMM) for SystemVerilog and allows designers to create complex protocol test scenarios for verifying their SoCs.

"The enterprise computing market is driving the need for the high-performance PCI Express 3.0 interface in the products our customers expect to be shipping in 2010," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "By providing designers with early access to PCI Express 3.0 IP that is based on a proven and trusted architecture, Synopsys lowers the risk of incorporating the PCI Express 3.0 interface into advanced SoCs."

Availability: Now

For more information visit: http://www.synopsys.com/