Synopsys optimized reference implementation methodology for ARM Processor-based Designs

Synopsys has announced that it has developed an optimized reference implementation methodology enabling 2GHz fully synthesizable ARM Cortex-A8 Processor at 540mW, and suitable for advanced mobile and consumer applications.

To achieve optimized results, Synopsys uses the latest capabilities in the Galaxy Platform including, library subset usage scenarios, delay performance versus cell area tradeoffs, cell placement density versus floorplan dimension tuning, leakage optimization techniques, multi-corner multi-mode (MCMM) optimization for better timing correlation and signoff optimization between IC Compiler and Prime Time, and the usage of the new clock tree synthesis capabilities together with intelligent user clock constraints. The Galaxy Platform is a key component of Synopsys' Eclypse Low Power Solution and the Lynx Design System.

The ARM Cortex-A8 processor optimized implementation offers greater than 2GHz in the typical corner on a 40nm process while consuming 0.24mW/MHz dynamic power and 57mW static power using less than 2% LVt cells.

"Our collaboration with Synopsys will enable our licensees to achieve the kind of high-performance they need while preserving energy efficiency to be competitive in their marketplace," said Eric Schorn, VP marketing, Processor Division, ARM. "This optimized reference implementation methodology combined with ARM Physical IP will enable our partners to introduce more compelling ARM processor-based mobile and consumer products."

"The latest results of our collaboration with ARM enable designers to take maximum advantage of the Galaxy Implementation Platform on designs using leading-edge ARM Cortex processor cores and Physical IP," said Dr. Antun Domic, senior vice president and general manager, Implementation group at Synopsys. "By making this methodology available through the Lynx Design System, we will help customers to achieve the lowest cost of design and fastest time-to-market for their next generation mobile SoC designs."

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