FPGA based broadcast connectivity targeted design platform with DisplayPort IP core

Xilinx has announced the availability of broadcast connectivity platform incorporating the new DisplayPort interface LogiCORE intellectual property (IP) core from Xilinx enabling transmission and reception of serial digital video for professional and consumer displays.

"SDI is ubiquitous throughout the broadcast industry today. Companies don't want to spend effort, time, and money on interfaces," said Ben Runyan, senior manager, Broadcast Marketing at Xilinx. "Our broadcast connectivity platform and DisplayPort IP simplify interface development, so manufacturers can improve time to market, lower implementation costs, and focus on creating value for their end customers. They can spend time finding innovative ways to differentiate and put limited engineering resources to better use developing advanced, higher quality video processing. These are compelling market advantages, especially for the many companies that already use Xilinx FPGAs in their broadcast systems."

The Xilinx said, this Broadcast Connectivity Targeted Design Platform encompasses all the connectivity elements needed by hardware and software developers to build serial digital interface (SDI) solutions to characterize and verify performance for the targeted applications. Developers can choose Virtex-6 FPGAs for the highest-speed serial connectivity with up to 72 serial transceivers and line rates in excess of 11Gbps for SD/HD/3G-SDI and embedded audio applications, integrated and supports for 10G SDI designs. For low risk and low cost serial connectivity, Spartan-6 FPGAs with up to eight 3.125Gbps transceivers support SD and HD resolution applications with up to 60 percent low system cost and less than 50 percent of the power.

Broadcast connectivity platform include Xilinx and third-party domain and application-specific IP cores, complete design environments, and demonstration and reference designs, along with a base set of digital audio/video development boards and industry-standard FPGA Mezzanine Card (FMC) daughter boards.

The Xilinx DisplayPort interface IP core supports the digital-video-I/O standard introduced by VESA (Video Electronics Standards Association) to provide higher resolution and richer color than traditional VGA or DVI interfaces. The scalable and extensible open-standard core is fully compliant with the DisplayPort version 1.1a specification. It provides a small design footprint that improves signal integrity and reduces EMI, while providing faster speeds and lower power. The features like content protection using HDCP are also part of the standard DisplayPort interface IP core.

Live demonstrations of the broadcast connectivity platform and DisplayPort IP are being held at the IBC2009 Exhibition in Amsterdam from September 11th through 15th in Xilinx Booth #10.B30.