MDDR memory controller IP core supporting 200 MHz Cyclone FPGAs

Microtronix has announced an upgrade of their Multi-port MDDR Memory Controller IP Core to support 200 MHz Mobile DDR (MDDR) memory devices in Cyclone II and Cyclone III FPGA devices from Altera.

The Microtronix MDDR Memory Controller IP Core is available with either a native Read and Write bus interface or an Altera Avalon bus for incorporation into Nios II soft-core processor systems. The cores support Cyclone, Stratix and Arria FPGA devices.

Microtronix SDRAM memory controller IP cores are targeted at high performance single and multi-port streaming data applications for high level of performance and reliability, the IP core deliverables include full Synopsis Design Constraint support for the TimeQuest timing analyzer and IP functional simulation models.

"The Microtronix MDDR Memory Controller IP Core enables design engineers to leverage the benefits of Mobile DDR devices in next generation embedded system." said Blair Bryce, Sales & Marketing. "For example: by switching existing design from DDR and DDR2 designs to MDDR devices they can minimize the power dissipation without sacrificing the clock speed of their memory system. They also benefit from the longer product life-cycle of MDDR devices compared with DDR and DDR2 consumer memory solutions."

For more details visit www.microtronix.com