Altera's RapidIO IP core qualifies RIOLAB device interoperability testing

Altera has announced its Serial RapidIO MegaCore intellectual property (IP), version 9.0, was qualified by RIOLAB's device interoperability level-3 (DIL-3) testing and ensures that Altera's internally developed Serial RapidIO IP is interoperable with components, systems and software using RapidIO technology. The IP core works with Altera's Arria, Cyclone, Stratix FPGAs and HardCopy ASICs.

Altera's Serial RapidIO MegaCore function is designed to the RapidIO interconnect specification version 1.3. The core supports x1 and x4 lane widths at 1.25-Gbps, 2.5-Gbps and 3.125-Gbps lane rates, and allows for physical-, transport- and logical-layer separation. The endpoint IP core comes complete with test benches that provide interoperability with digital signal processor and switch vendors.

"Serial RapidIO is the interconnect technology of choice for many wireless, military and medical system designers who require a high level of security, data management and quality of service," said Luanne Schirrmeister, senior director of component product marketing at Altera. "For these designers, passing RIOLAB's DIL testing gives them the added confidence that Altera's devices and RapidIO IP core are compatible and interoperable within their RapidIO system."

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