Synphony HLS product from Synopsys now support Xilinx Virtex-6 FPGAs

Synopsys has announced that its Synphony HLS (High Level Synthesis) product now includes optimized support for Xilinx Virtex-6 FPGAs. The HLL flow is said to provide Virtex-6 FPGA users with more automatic target-specific optimizations and architecture exploration from high level models and deliver up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications.

The Synphony HLS product generates RTL for Virtex-6 FPGA implementation as well as testbench scripts to verify that the RTL implementation. Synphony HLS also generates fixed-point C-models that can be used for system validation and functional verification.

"The Synphony HLS solution combined with the Virtex-6 and Spartan-6 families' Targeted Development Platforms has significantly reduced the effort required to get signal processing algorithms running on high-performance FPGA technology," said Tom Hill, senior manager DSP platforms at Xilinx. "The Synphony HLS product complements existing flows by providing a very high level of design abstraction with architecture exploration features and world-class quality of results for design teams developing wireless infrastructure, broadcast, industrial, military and aerospace applications."

"The growing number of opportunities created by today's DSP-rich FPGAs further widens the design productivity gap compared to implementing systems with high-end DSPs," said Johannes Stahl, marketing director for system-level solutions at Synopsys. "Using Synphony HLS with Xilinx Virtex-6 FPGAs addresses this gap by allowing design teams to more rapidly create, optimize, explore and verify complex algorithms, such as orthogonal frequency division multiplexing (OFDM) and multiple-input multiple-output (MIMO) modems that are now frequently being used in wireless and broadcasting designs."

To know more visit: http://www.synopsys.com