Actel's new Libero IDE v8.6 for Low Power Design and Analysis

Actel has released the Libero Integrated Design Environment (IDE) v8.6 for low-power designs and analysis. This new Libero IDE features include upgraded power analysis using the SmartPower tool and post-layout probe insertion for device debug.

SmartPower v8.6 with a new design analysis algorithm that provides a quick and accurate method for performing power analysis without the need of Value Change Dump (VCD) file. The new I/O Advisor identifies and suggests an I/O configuration that provides the least power consumption while meeting timing constraints. For efficient design and debug, the new post-layout probe insertion feature allows to bring signals out to package pins for observation without needing to instrument within the design RTL and go through the synthesis flow.

"Power consumption is now the number one design consideration in many markets and applications, ahead of performance and cost", said Jim Davis, vice president of software and systems engineering. "With the enhanced features included in release 8.6, Actel strengthens its industry leading solutions for power optimization and analysis, and improves design cycle efficiency with easy to use probe insertion and signal observability".

In SmartPower, the new vectorless power estimation provides power consumption results approaching the accuracy of a simulation derived VCD file in considerably less time. In the absence of simulation data, this feature provides better activity estimation than the default toggle rate method. And the I/O Advisor analyzes a design and suggests alternate output loads, drive strengths, and slew rate, reduces I/O power consumption. The power consumption data is reported for both the current as well as the proposed options so the designer can easily ascertain the impact on power for the suggested alternatives. Designers can now test "what-if" scenarios to modify slew rates, drive strengths, and output loads in order to discern the optimal balance between power and timing.

For design debug, the probe point insertion feature enables to insert probes into the design after layout and bring signals out to package pins for analysis. Specific nets or clocks within the design can have probes added, edited and deleted. This real-time capability to view signals greatly enhances a designer's capability to pinpoint logic or timing problems. After the evaluation, the designer can easily revert back to the original saved design. The new debug methodologies require the designer to instantiate logic and probes within the design RTL and then run the design through synthesis and layout, which requires a substantial increase in debug time and system time to market.

Availability: All editions are one-year renewable licenses.
Libero IDE: Can be downloaded from Actel's website.
Actel Libero IDE Gold edition: available on Windows XP or Vista free of charge.
Actel Libero IDE 8.6 Platinum edition: available on Windows and Linux platforms for $2495.

For more details visit: http://www.actel.com/products/software/libero/default.aspx