Clock ICs from ADI to improve performance

Analog Devices has introduced two clock products that, when designed in as part of a complete timing signal chain, improve performance and reduce programming and design complexity in synchronous optical networks and wireless base stations. They are:

--The AD9553 clock generator is recommended for low-cost clock translation needs in GPON, SONET/SDH OC-48 (synchronous optical networking/synchronous digital hierarchy), test and measurement, data acquisition, Ethernet, Fibre Channel, T1/E1, broadcast video and other wireless and wired communications applications.

--The ADCLK944 is designed to improve SNR (signal-to-noise ratio) performance from data converters in wireless base stations as well as provide low-power, low-jitter performance for SONET/SDH optical networks.

AD9553:

The AD9553 clock generator consists of pre-set input/output frequency ratios that can be easily pin-programmed. The pin-programming mode provides a matrix of standard input/output frequency translations, while a SPI (serial peripheral interface) port is available to program customized input-to-output frequency translations. It also features jitter clean-up and clock translation. The input/output clock frequency combinations and its output stage flexibility eliminate up to two discrete PLLs (phase-locked loops) and various other discrete components, reducing board space, design complexity and simplifying programming. It also has a holdover mode that provides output signals even in the absence of a reference input. If one of the CMOS references fails, the clock generator also includes a switchover function that provides additional security without losing the lock on downstream PLLs.

ADCLK944:

The ADCLK944 clock fanout buffer feature a jitter figure of 50-fs (femto seconds) for communications equipment that require multiple high-performance clock signals without compromising high-speed signal conversion in LTE, MC-GSM and other wireless network applications. Its jitter performance combined with low power consumption per channel made it effective for applications based on the Gigabit Ethernet (GbE) and SONET/SDH optical network multiplexing protocols. Its low jitter allows design flexibility for the SerDes (serializer/deserializer) clock designer. Due to its low power consumption it finds use in high-density SONET boards containing multiple channels.

The ADCLK944 clock fanout buffer provides four LVPECL outputs that operate at speeds up to 7 GHz and can achieve broadband random rms (root-mean square) additive jitter of 50 fs. It has a low jitter and maxoutput-to-output skew of 15 ps (pico seconds) and is designed for wired and wireless equipment that require clean clock signals for high-speed converter clocking, such as LTE and multi-carrier GSM communications base stations. It also contributes to addressing clocking-distribution jitter generation requirements for OC-192 and OC-768 SONET line cards. Its low-noise performance enables high SNR levels, particularly when designed as part of a complete signal chain incorporating DACs (digital-to-analog converters), ADCs (analog-to-digital converters) and clock generators. It is designed to operate with ADI's AD9779 Dual 16-Bit, 1 GSPS DAC, AD9739 14-Bit, 2500 MSPS, RF DAC and AD9789 14-Bit, 2400 MSPS TxDAC+ with 4-Channel Signal Processing and ADCs such as the AD9445 14-Bit, 105 MSPS / 125 MSPS and AD9446 16-Bit, 80 MSPS / 100 MSPS.

Product Sample Availability Temperature
Range Price Each
Per 1,000 Packaging

AD9553 NOW -40°C to +85°C $5.10 5 mm x 5 mm
32-lead LFCSP

ADCLK944 NOW -40°C to +85°C $6.00 3 mm x 3 mm
16-lead LFCSP

For more information visit: http://www.analog.com