Altera's new 28nm Stratix V FPGAs for silicon hungry applications

Altera is in design-ready mode for its new 28-nm Stratix V FPGA family, which is expected to be available in volumes by early 2011. Altera is advising FPGA designers who need more silicon horse-power to start designing using 28nm FPGAs now itself to gain the benefits of Moore's law as well as some more features added to this new family. The highlight of this 28nm FPGA family is, it features industry's highest bandwidth with speeds up to 1.6 Tbps.

The Stratix V FPGA has 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18x18 multipliers and integrated transceivers operating up to 28 Gbps. These chips pack more hard-IPs compared to previous generation FPGAs to provide the designer with higher performance and faster development. This family is targeted for high-end applications requiring more silicon and speed such as wireless/wireline communications, military, broadcast, computer and storage, test and medical markets.

28-nm Stratix V FPGA family is available in 4 variants, they are:

1. Stratix V GT FPGA with integrated 28-Gbps transceivers for high speed apps.

2. Stratix V GX FPGA is for wide range of applications with 600-Mbps to 12.5-Gbps transceivers.

3. Stratix V GS FPGA is for DSP applications with 600-Mbps to 12.5-Gbps transceivers.

4. Stratix V E FPGA with high logic gate density is for ASIC prototyping and computing applications.

The other key features of this family include:
1. Direct interoperability to 10G backplanes (10GBASE-KR) and optical modules.
2. Stratix V FPGAs include a 7 x 72-bit 1,600-Mbps DDR3 memory interface and LVDS channels operating at 1.6 Gbps on ubiquitous I/Os.
3. Variable-precision DSP block to perform across multiple-precision DSP data paths.
4. User friendly partial reconfiguration feature

Hardened IP functions in the device include PCIe Gen3, Gen2, Gen1, 40G/100G Ethernet, CPRI/OBSAI, Interlaken, Serial RapidIO (SRIO) 2.0 and 10 Gigabit Ethernet (GbE) 10GBASE-R. Memory interfaces with hardened read/write paths include DDR3, RLDRAM II and QDR II+.

To know more visit www.altera.com/stratix5