140mW/channel quad 14-Bit, 125Msps ADCs from Linear

Linear has announced a family of 24 ultralow power 14-bit/12-bit, 125Msps to 25Msps, quad and dual ADCs that dissipates one-third the power of competing ADCs. The flagship ADC is the LTC2175-14, a quad 14-bit, 125Msps ADC that dissipates 558mW (140mW per channel).

The LTC2175 offers signal to noise ratio (SNR) performance of 73.4dB and spurious free dynamic range (SFDR) of 88dB at base band. Operating from 1.8V analog and digital supplies, the LTC2175 includes a sleep mode that reduces power dissipation to 1mW. Whether operating at full speed or in sleep mode, this ADC significantly lowers the power budget for high-speed multichannel designs such as multiple-input multiple-output (MIMO) WiMAX/LTE and 3G base stations, portable medical imaging and non-destructive testers.

The output data from the LTC2175 is in serial LVDS format to minimize the number of data lines. At 125Msps, each channel outputs two bits at a time, using two lanes per ADC. At lower sample rates, a one bit per channel option is available.

The LTC2175 includes a SPI-compatible interface. Options include a data output randomizer that reduces digital feedback, seven programmable LVDS output current levels, internal 100Ohm LVDS output termination resistors, and digital output test patterns. These settings can be programmed via SPI or hard-wired for a reduced set of operating modes.

Some more features of these devices are,

Single 1.8V Analog & Digital Supplies
Selectable Input Ranges: 1VP-P to 2VP-P
800MHz Full-Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer

Package:

Pin Compatible 14-Bit and 12-Bit Versions
Quad Versions: 52-Pin (7mm x 8mm) QFN Package
Dual Versions: 40-Pin (6mm x 6mm) QFN Package

Availability: by October.

For more details visit www.linear.com.

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