Date: 29th July 09

 Altera and Xilinx announce FPGA devices with PCI Express transceivers

The top-2 programmable logic semiconductor vendors Xilinx and Altera have announced in this week their new FPGA devices supporting PCI Express bus interface.

Altera said its 40-nm Arria II GX FPGAs are compliant with the PCI Express (PCIe) 2.0 specification. The Arria II GX FPGAs have successfully passed the PCI-SIG Compliance and Interoperability tests at the PCI-SIG workshop and is now included on the PCI-SIG Integrators List. Arria II GX FPGAs achieved compliance for up to x8 lane configurations for PCIe Gen1 end-point applications.

Immediately available Arria II GX FPGAs pack transceivers with data rates up to 3.75 Gbps, and have a hard, configurable PCIe interface embedded within the device. The device's hard IP block implements PCIe Gen1 (PIPE) PHY-MAC, data link, and transaction layers.

"Arria II GX FPGAs are the only mid-range FPGAs that have attained PCIe 2.0 compliance," said Luanne Schirrmeister, senior director of component product marketing at Altera. "They offer 25 percent higher performance, up to 50 percent lower price and up to 50 percent lower power compared to competitive FPGAs."

Arria II GX FPGAs are targeted for applications using mainstream protocols such as PCIe and Gigabit Ethernet (GbE). The devices have up to sixteen 3.75-Gbps transceivers, 256K logic elements (LEs) and 8.5 Mbits of internal RAM.

For more details visit www.altera.com/products/devices/arria-fpgas.

Xilinx has also announced its Virtex-6 FPGA family compliant with the PCI Express 2.0 specification and has passed PCI-SIG PCI Express version 2.0.

PCIe 2.0 blocks are integrated in all Virtex-6 devices with serial transceivers and are supported in all speed grades. These blocks include the complete transaction data link and physical layers, which use the Xilinx GTX transceiver technology and integrated BRAM. The GTX serial transceivers in Virtex-6 LXT and SXT FPGAs are fully characterized across process, voltage and temperature (PVT), and the complete PCI-SIG compliance report is available for download at: www.pcisig.com/developers/compliance_program/integrators_list/pcie_2.0

"With increasing adoption of PCIe Gen 2 for meeting high bandwidth connectivity requirements, many of the VLSI/System design houses in India are increasingly engaging global customers in use of this protocol as part of their overall system designs," said Neeraj Varma, Country Manager - Sales, for India and Australia and New Zealand at Xilinx. "By offering this as Hard IP in Virtex-6 along with reference designs, the design houses in India can offer a very compelling solution to their end customers - by reducing the overall project timeline along with the total cost of ownership".

"The demand for high-bandwidth connectivity is insatiable, and the PCIe 2.0 standard is critical to meeting the requirements of high performance, low power applications, especially in the telecommunications and server markets," said Tom Feist, senior marketing director for ISE Design Suite at Xilinx. "Integrated PCIe FPGA blocks eliminate the I/O bottleneck in maximizing system performance, and were first introduced with our Virtex-5 FPGAs. Now with Virtex-6 FPGAs, designers in the pursuit of even higher bandwidth can take full advantage of our production-proven PCIe implementation with up to 50 percent lower power than the nearest competitive offering."

Both Xilinx and Altera provide exhaustive support to FPGA design engineers with tools, software, boards, reference designs, ready IP cores and learning tutorials

For further details on Xilinx PCIe products visit: www.xilinx.com/pciexpress

 

.