Silicon Frontline's new version of its post-layout EDA tool is 10x more powerful

Silicon Frontline Technology is shipping new version of its flagship post-layout verification products, F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices. F3D targets VLSI design of analog and mixed signal semiconductor ICs and R3D targets power devices.
Silicon Frontline claims the new version of F3D improves its performance by up to 10x when compared to the previous version. F3D and R3D also accommodate larger designs than the previous versions announced in May 2009.

According to Dermott Lynch, VP Marketing at Silicon Frontline, "To address our customers' post-layout verification needs as their technology options change, we are focused on improving our software products' performance and our products' capacity to handle full-chip designs."

F3D is recommended for post layout verification part of VLSI design process while designing nanometer and analog mixed signal semiconductor ICs and R3D for its ability to improve the reliability and efficiency of semiconductor power devices.

F3D and R3D incorporate patent-pending 3D technology to improve the accuracy of full-chip post-layout verification.

The new version of F3D accomplishes full chip extraction of a 65nm SOC in under 2 hours compared to 10 hours in previous version. The MOMCaps run in under 1 minute compared to 3 minutes in the previous version. This said to be huge improvement over most commercial Field Solvers

The new tiling feature allows design size for F3D and R3D to be unlimited. Designs can be automatically partitioned into blocks of up to 4-million transistors and each block can be run using one CPU or multiple CPUs can run a number of design blocks in parallel. In the previous version the block size was limited to a maximum of 1-million transistors.

Silicon Frontline claims these results are not possible with commercial tools available today. For a 40nm design F3D delivered results within 2% of silicon, competing tools were up to 30% off.

Silicon Frontline says major foundries have qualified its software. They are used for designs that target mature process technologies or advanced process technologies such as low as 28nm.

For details visit www.siliconfrontline.com